1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method of controlling an operating voltage for the semiconductor integrated circuit.
2. Description of Related Art
A reduction in the operating voltage or the operating frequency is effective in reducing a power consumption in a semiconductor integrated circuit. To achieve this, a dynamic voltage and frequency scaling (DVFS) that reduces the power consumption by dynamically controlling the operating frequency of a circuit and a supply voltage has been generally known. For example, a technique in which operation switches between one operation mode for prioritizing an operating speed and another operation mode for prioritizing a low power consumption to achieve a low power over the entire operation for a long period of time is disclosed in Burd, T., Pering, T., Stratakos, A., Broadersen, R.: “A Dynamic Voltage Scaled Microprocessor System”, 2000 IEEE International Solid-State Circuits Conference 07803-5853-8/00.
In this document, the operating voltage is changed according to a difference between a frequency of a clock signal from an oscillator and a requested clock frequency. As a result, circuit operation can be conducted at a desired frequency.
As a technique for controlling a supply voltage, for example, Japanese Unexamined Patent Publication No. 2000-216337 and Japanese Unexamined Patent Publication No. 2009-200739 have been known. Japanese Unexamined Patent Publication No. 2000-216337 discloses a device for controlling the supply voltage according to the amount of delay of a replica circuit. Japanese Unexamined Patent Publication No. 2000-216337 also discloses that when the lowest voltage that enables a circuit located at a center of a process variation to normally operate is set as an initial value, a convergence time on the optimum supply voltage is shortened. Also, Japanese Unexamined Patent Publication No. 2009-200739 discloses a semiconductor integrated circuit that steps down the supply voltage across a path having a delay margin in a critical path to reduce the power.
Further, there has been known a technique in which the operating voltage is controlled to compensate the process variation. For example, U.S. Patent No. 2009/0077514 discloses a technique for conducting a design assuming a voltage control for compensating the process variation.